The demands for highly efficient digital equipment continue to increase, and there is strong need to embed high-speed and low-power-consumption memory into SoC (system-on-chip). Since conventional memories such as SRAM, DRAM, and flash are unsuitable choices for these applications, one unique memory, Direct Tunneling Memory (DTM), with ultra-thin tunnel oxide and novel depleted floating gate is developed for cost-effective and scalable embedded RAM applications. The features of the DTM structure include sidewall control gates fabricated on both sides of a floating gate, and offset source/drain regions without overlapping the floating gate. Its simple fabrication process is fully compatible with the existing CMOS logic technology, and its simple structure can obtain sufficient tunnel current at higher speed operation and lower operating voltage than conventional flash memory.
FIG. 1 is a cross-sectional diagram illustrating a high-speed RAM with sidewall control gates fabricated by a conventional polysilicon spacer process. In general, a gate oxide layer 12, a first polysilicon layer 14 and a hard mask layer 16 are successively deposited on a semiconductor substrate 10, and then the first polysilicon layer 14 is patterned to form a floating gate 14 from the use of photolithography and etching process. Next, a thin silicon oxide layer 18 is thermally grown on the substrate 10 and sidewalls of the floating gate 14. Then a second polysilicon layer 20 is deposited followed by an anisotropic etch-back process, which forms sidewall control gates 20 on both sides of the floating gate 14. The thin oxide layer 18 is also etched through, leaving this thin oxide layer 18 only underlying the sidewall control gates 20.
The conventional anisotropic polysilicon etch process, however, can not well control the dimensions and profiles of the sidewall control gates to facilitate proper device design. The width of polysilicon spacer, referred to the control gate width, may vary to a large extent in a wafer or from wafer to wafer. The variation in the spacer width is also unfavorable to subsequent contact process, and therefore an additional polysilicon line is needed for the contact formation, which leads to increase in memory cell size and difficulty in layout design. Moreover, the anisotropic etch back may round corners of the polysilicon spacers, thus a subsequent silicidation process, for reducing the RC time constant and improving operations of reading, programming, and erasing, can not be perfectly performed in the rounded-shaped control gates.